Instruction Cycle and And Timing Diagrams For 8085

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Instruction Cycle

The time required to fetch an instruction and necessary data from memory and to execute it, is called an instruction cycle. Or the total time required to execute an instruction is given by:

 Where,
  

Timing Diagram for Instruction Cycle

• Fetch the instruction (Fetch Cycle)

In the beginning of the fetch cycle, the content of the program counter (PC), which is the address of the memory location where opcode is available, is sent to the memory. The memory puts the opcode on the data bus so as to transfer it to the CPU.
The whole operation of fetching an opcode takes three clock cycles. A slow memory may take more time.

• Decode the instruction (Decode Cycle)

The opcode fetched from the memory goes to the data register, DR and then to instruction register, IR. From the IR it goes to the decoder circuitry which decodes the instruction. Decoder circuitry is within the microprocessor.

• Execute the Instruction (Execute Cycle)

After the instruction is decoded, execution begins.
If the operand is reside the general purpose registers, execution is immediately performed. The time taken in decoding and execution of an instruction is one clock cycle.
In some situations, an execute cycle may involve one or more read or write cycles or both.
Read Cycle: If an instruction contains data or operand address which are in the memory, the CPU has to perform some read operations to get the desired data. In case of a read cycle the instruction received from the memory are data or operand address instead of an opcode.
Write Cycle: In write cycle data are sent from the CPU to the memory or an output device.

• Machine Cycle and State

The necessary steps carried out to perform the operation of accessing either memory or input output device, constitute a machine cycle. In other words, necessary steps carried out to perform a fetch, a read or a write operation constitutes a machine cycle.
One sub-division of an operation performed in one clock cycle is called a state or T-state. In short, one clock cycle of the system clock is referred to as a state.

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Timing Diagram

The necessary steps carried out in a machine cycle can be represented graphically. Such a graphical representation is called timing diagram. The timing diagram for opcode fetch, memory read, memory write, I/O read and I/O write will be discussed below:

• Timing Diagram for Opcode Fetch Cycle:

• Timing Diagram for Memory Read

• Timing Diagram for Memory Write

• Timing Diagram for I/O Read

• Timing Diagram for I/O Write

In the above diagrams, the basic used parameters are:

ALE: ALE indicates the availability of a valid address on the multiplexed address/data lines. When it is high or 1, then it acts as an address bus and when low or 0, then it acts as a data bus.
RD (low active): If it is high or 1, then no data is read by the microprocessor. If signal is low or 0, then data is read by the microprocessor.
WR (low active): If it is high or 1, then no data is written by the microprocessor. If signal is low or 0, then data is written by the microprocessor.
IO/M (low active): A high or 1 on this signal indicates I/O operation while a low or 0 indicates memory operation.
S₀, S₁: S0 and S1 Indicate the type of machine cycle in progress.
The below table, shows the status of different control signal for different operation: